CMOS Transimpedance Amplifier

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          Used as the input of an optical receiver chain, a transimpedance amplifier is a current to voltage converter, often using a photodiode’s current as its input and converting it to a voltage, with it then amplifies, with gain and bandwidth specified by the needs of the system.

           The simplest current-to-voltage component is simply a resistor, in accordance with Ohm’s Law: V = I * R, where the resistance is analogous to the gain of the system. For this reason, the gain of a transimpedance amplifier is expressed in Ohms (Ω). However, simply using a resistor for this purpose comes with a set of issues. A large resistor means a large gain, but the inherent capacitance of a photodiode will result in a very slow response, proportional to the large R*C time constant. Attempting to minimize the time constant can only be done by lowering R, which in turn, lowers the gain.

         The requirements for this design, a project in an Analog IC Design course, were as follows: 150 kΩ of gain, an upper -3db bandwidth of minimum 150 MHz, and a lower -3db bandwidth of maximum 10 MHz, a max power consumption of 25 mW, an output peak to peak voltage swing of minimum 1.5V, and total input referenced current noise of less than 100 nA. Lastly, the amplifier would be met with a load with an impedance of 300 Ω at each output (600 Ω differential).

         The design of this transimpedance amplifier may be broken down in accordance to all of the tasks that it needs to accomplish. The design first requires an input stage, to set a wide bandwidth and reasonable gain to use as the foundation of later stages. A shortcoming in either of these categories would become more and more difficult to overcome later on in the design. The single ended signal, at some point, must be used as the input to a differential amplifier, as a differential output signal is required. Lastly, an output stage is required to manage the low differential load impedance of 300 Ω. Beyond these three requires stages, other stages would be added in to help with gain and bandwidth as necessary.

          The two choices, as commonly seen in literature, for the input stage were a common gate amplifier, or a regulated cascode amplifier, using the configurations as seen in Figure 1 and Figure 2. The goal of this stage was to accomplish as wide of a bandwidth, and as high of a gain, as possible. Testing of different configurations and values lead to the final choice of the input stage to be a regulated cascode, due to the high bandwidth and high gain that it provided. Before being connected to any future stages, which would act as a further ‘load’, the RGC configuration chosen provided a gain of approximately 80 dB, and a bandwidth of nearly 500 MHz. The bandwidth of the first stage would be the greatest possible bandwidth achievable - no later stage would allow for the bandwidth to increase past this point. On that logic, it was imperative that the bandwidth be as large as possible to account for any later stage that greatly detracts from it. After settling on a configuration, it was determined that no common gate, or other modification to the RGC, were able to provide better performance for either of those specifications. A DC source added along the signal path, for biasing purposes.

          The two remaining requirements for the design were a differential amplifier, and an output stage. While stages may be requires between the input and these two required stages, that could not be assessed until the behavior of the two final stages was assessed.

          The output stage for this design was chosen as a common drain amplifier, due to its low output impedance, for use with the 300 Ω load. Using any other common configuration, such as a common gate or common drain, with such a low load, would result in a severe loss of gain. The common drain’s low output impedance and voltage follower characteristics made it an excellent choice as an output stage. However, in the presence of the body effect, the gain of the common drain amplifiers would be <1. The gain can be approximated as gm/(gm+gmb), where gm is the transconductance of the common drain’s main MOS device and gmb is the backgate transconductance, or the transconductance associated with the bulk of the device. Knowing this, the previous stages would have to be designed to accomodate for the drop in gain that the common drain would provide. The required gain across the flat band of the circuit’s AC response is 150 kΩ, which corresponds to a gain of 103.52 dB. Knowing this, and trying to account the gain drop due to the common drain, the gain up until this stage must lie  >110 dB, or even larger is the common drain is not optimized to have the minimum possible drop across it.

          With a gain of ~80 dB after the regulated cascode and a goal of 110 dB before the common drain, a simple differential amplifier would not suffice to provide the required gain, as 30 dB of gain for a single stage would be a lofty goal while maintaining bandwidth and stability.  A common source stage would need to be implemented between the input stage and the differential pair, as a common source amplifier would be an optimal choice to provide the necessary gain. Putting the common source amplifier before the differential pair would be a great deal easier than putting it after the differential pair, as the common source itself would then have to be differential, to maintain signal integrity. In practice, two cascaded common source amplifiers were chosen to be placed between the input RGC stage and the differential pair. Each gain stage (the two common source stages and the differential pair) slowly increased the gain to an acceptable level before the drop across the common drain amplifier, all while building off of the wide bandwidth and gain that was set originally by the regulated cascode input stage.  Following this general topology, the requirements could be met.

          To cascade the stages together, each stage was connected to the next via a large capacitor, each known as “Cbig”. These large capacitors blocked the DC voltage from the output of one stage from reaching the next, but allowing the signal to pass through and maintain its integrity. In order to bias all transistors after the first stage, after each instance of Cbig, a voltage divider was implemented., consisting of two resistors in series, with VDD connected at the top of one, and ground connected to the bottom of the other. The output was taken between the two resistors, and adjusting the values of the resistance allowed for control of the gate voltage of the transistor connected to this ‘biasing network’.   

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          The circuit achieved the following specs: 307.26 kΩ of gain, upper cutoff frequency of 158.8 MHz, a lower cutoff frequency of 106.8 kHz, a power consumption of 16.59 mW, an output peak to peak voltage swing of 1.494 V, and total input referenced current noise of 22.6 nA.